Differential comparator for amplifying small swing signals to a full swing output

ABSTRACT

A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.

FIELD OF THE INVENTION

The present invention relates generally to comparator circuits and moreparticularly to differential comparator circuits that amplify smallswing input signals to full swing output signals.

BACKGROUND OF THE INVENTION

A differential comparator is often used in clock acquisition circuitssuch as delay-locked loops (DLL) and phase locked loops (PLL) to comparethe value of a voltage at a first terminal of the differentialcomparator to the value of a voltage at a second terminal of thedifferential comparator. For some applications, the signals provided atthe inputs of the differential comparator are "small swing" signals thathave small amplitudes relative to the supply voltage levels. Forexample, for CMOS circuits wherein the supply voltage VCC is equal 3.3volts and system ground VSS is equal to zero volts, a small swing signalmay have an amplitude of 0.5 volts that swings between a low of 1.5volts and a high of 2.0 volts. A "full swing" signal swingsapproximately between 3.3 volts and zero volts (ground).

Clock acquisition circuits are typically used to clock the circuitry ofan integrated circuit, and the differential comparator must output fullswing signals to drive the integrated circuit. The differentialcomparator circuit must therefore provide gain to amplify the smallswing input signals to a full swing output signal. For higher frequencyapplications, it is difficult to provide the necessary gain using priordifferential comparators.

SUMMARY AND OBJECTS OF THE INVENTION

Therefore, it is an object of the present invention to provide adifferential comparator that amplifies small swing signals into fullswing signals.

It is a further object of the present invention to provide a CMOSdifferential comparator that amplifies small swing input signals to fullswing output signals at higher frequencies.

A differential comparator that amplifies small swing signals to fullswing signals is described. The differential comparator comprises acurrent switch having a pair of inputs coupled to receive a pair ofsmall swing complementary input signals and a pair of complementaryoutputs that output complementary signals. The complementary signalsoutput by the current switch have a voltage swing that centers about apredetermined voltage in response to the complementary input signals.The differential comparator further comprises first and second inverterscoupled to receive the complementary signals, wherein each inverter hasa trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to thepredetermined voltage. The first and second inverters output full swingcomplementary output signals in response to the complementary signals.

Because the outputs of the current switch center about the trip pointvoltage of the inverters, the inverters provide a current path betweenVCC and VSS during normal operation. According to one embodiment, thedifferential comparator includes circuitry for disabling thedifferential comparator during a power-down mode of operation such thatthe differential comparator draws little or no current. Part of thisfunctionality is provided by designing the inverters to be tri-statable.The need for additional disabling circuitry for disabiling the currentswitch, is dictated by the circuit topology of the current switch.

Other objects, features, and advantages of the present invention will beapparent from the accompanying drawings and from the detaileddescription which follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not by way oflimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements, and in which:

FIG. 1 shows a differential comparator according to one embodiment.

FIG. 2 shows a voltage generator that supplies a trip point voltageV_(TR).

FIG. 3 shows a tri-statable inverter according to one embodiment.

FIG. 4 shows a differential comparator as including a bias circuit.

DETAILED DESCRIPTION

A differential comparator according to the present embodiments quicklyamplifies small swing differential input signals to generate full swingcomplementary output signals. The differential comparator generallycomprises an input stage, a gain stage, and an output stage. The gainstage generally comprises inverters each having a trip point voltage ofV_(TR). The input stage acts as a current switch that outputscomplementary output signals each having a voltage swing that centersabout the trip point voltage V_(TR). Centering the output signals of theinput stage about the trip point voltage V_(TR) enables the inverters ofthe gain stage to switch on and off quickly to provide full swing outputsignals. The output stage provides additional gain.

FIG. 1 shows a differential comparator 100 according to one embodiment.Differential comparator 100 comprises an input stage 110, a gain stage120, and an output stage 130 coupled in series. Input stage 110 acceptssmall swing differential input signals V_(in+) and V_(in-). Theamplitude of the differential input signal V_(in) may be, for example,0.5 volts. Input stage 110 provides a modest gain, and output signals ofinput stage 110 are provided via output nodes A and B to gain stage 120,which amplifies the output signals of the input stage 110 into fullswing signals. Output stage 130 provides further gain, speeding thetransitions between the rail voltages and providing sufficient outputcurrent to drive the capacitive load of the remaining portions of theintegrated circuit.

Input stage 110 is shown as a common source differential amplifier thatoperates as a current switch wherein a current having a value of 2I₁ isswitched between the transistors of the differential amplifier.Alternative current switch and differential amplifier architectures maybe used. Input stage 110 includes a differential pair of NMOStransistors 111 and 112, each having their sources coupled to systemground VSS via a common node N and current source 115 and their drainscoupled to the supply rail VCC via current sources 113 and 114,respectively. Current sources 113 and 114 are each selected to source acurrent having a value of I₁, and current source 115 is selected to sinka current having a value of twice I₁. Output node A is taken at thedrain of transistor 112, and output node B is taken at the drain of node111.

Resistors R1 and R2 having equal values are coupled in series betweenoutput nodes A and B. A trip point supply voltage V_(TR) is provided atthe common node between resistors R1 and R2. The trip point supplyvoltage V_(TR) causes the output voltages at output nodes A and B tocenter around the trip point supply voltage V_(TR). The output voltageat each output node of the input stage 110 is approximately (V_(TR) ±I₁R), wherein R is the value of each of the transistors R1 and R2. WhereinVin+>Vin-, the voltage at output node A is approximately (V_(TR) +I₁ R),and the voltage at output node B is approximately (V_(TR) -I₁ R).Conversely, wherein Vin+<Vin-, the voltage at output Node A isapproximately (V_(TR) -I₁ R), and the voltage at output node B isapproximately (V_(TR) +I₁ R).

Gain stage 120 comprises a first input inverter 121 having its inputcoupled to output node B and a second input inverter 122 having itsinput coupled to output node A. Both input inverters are CMOS inverters.The value of trip point supply voltage V_(TR) is selected to be thevalue of the trip point voltage of input inverters 121 and 122 such thatinverters 121 and 122 switch on and off quickly.

Because the output voltages of input stage 110 center about the trippoint voltage of input inverters 121 and 122, input inverters 121 and122 can change states quickly. Unfortunately, the MOS transistors ofinverters 121 and 122 are never fully switched off. To reduce the powerconsumption of input inventers 121 and 122, input inverters 121 and 122are tri-statable. Each input inverter therefore includes an enable inputcoupled to receive an enable signal EN for coupling and decoupling theinverters from the supply rails. The enable signal may be deassertedlow, for example, when the integrated circuit and differentialcomparator are to be placed in a power-down mode wherein powerconsumption of differential comparator 100 is reduced. As will bedescribed with respect to FIG. 4, differential comparator 100 draws nocurrent when operating in the power-down mode.

Cross-coupled inverters 123 and 124 are provided to improve the powersupply rejection of differential comparator 100. Disturbances in thepower supplies of input inverters 121 and 122 may result in one of theoutput signals of the input inverters beginning to switch between railvoltages before the other output signal. Cross-coupled inverters 123 and124 compensate for this effect. Inverter 123 has its input coupled tothe output of input inverter 121 and its output coupled to the output ofinput inverter 122. Similarly, inverter 124 has its input coupled to theoutput of inverter 122 and its output coupled to the output of inverter121. The cross-coupled inverters help to ensure that the differentialoutput voltages of gain stage 120 cross approximately at the thresholdvoltage V_(TR).

Cross-coupled inverters 123 and 124 need not provide as much current asinput inverters 121 and 122. Therefore, according to one embodiment, thechannel widths of the CMOS transistors of cross-coupled inverters 123and 124 are approximately 20% of the channel widths for input inverters121 and 122. Cross-coupled inverters 123 and 124 may also betri-statable.

Output stage 130 comprises inverters 131 and 132. The input of inverter131 is coupled to the output of inverter 121, and the input of inverter132 is coupled to the output of inverter 122. Output inverters 131 and132 provide additional gain and provide sufficient current to drive thecapacitive load of an integrated circuit coupled to the outputs ofdifferential comparator 100. Output inverters 131 and 132 may also betri-statable.

FIG. 2 shows a voltage generator 200 that supplies the trip pointvoltage V_(TR). According to the present embodiment, centering voltagegenerator 200 comprises an inverter 210 having the same operatingcharacteristics as input inverters 121 and 122 wherein inverter 210 hasits output coupled to its input. The use of matching inverter 210 makesthe centering voltage generator 200 less susceptible to processvariations that affect the trip point voltages of input inverters 121and 122.

FIG. 3 shows a tri-statable inverter 300 according to one embodiment.Tri-statable inverter 300 generally comprises a CMOS inverter whichincludes a PMOS transistor 301 and an NMOS transistor 302 having theirgates commonly coupled to an input node and their drains commonlycoupled to an output node. The source of PMOS transistor 301 is coupledto VCC via PMOS transistor 303, and the source of NMOS transistor 302 iscoupled to system ground VSS via NMOS transistor 304. The enable signalEN is coupled directly to the gate of transistor 304 and to the gate oftransistor 303 via inverter 305 for removing the conductive path betweenVCC and VSS when it is desirable to reduce the power consumption ofdifferential comparator 100. When the enable signal EN is logic low(deasserted), transistors 303 and 304 are switched off. Tri-stableinverter 300 operates as a normal CMOS inverter when enable signal EN islogic high (asserted). Enable signal EN may alternatively be provided asan active low signal.

FIG. 4 shows differential comparator 100 as further including a biascircuit 400 for ensuring proper current values of current sources 113,114 and 115 and for switching off the current sources when differentialcomparator 100 is placed in the power-down mode. According to oneembodiment, current sources 113 and 114 are matched PMOS transistors,and current source 115 is an NMOS transistor. Bias circuit 400 providesbiasing current to the gates of transistors 113, 114 and 115 such thattransistors 113-115 conduct the appropriate amount of source-draincurrent.

Bias circuit 400 generally comprises a pair of differential inputtransistors 411 and 412 that are approximately half the size oftransistors 111 and 112 of input stage 110. The gates of transistors 411and 412 are coupled to differential input voltages V_(in+) and V_(in-),respectively. The sources of transistors 411 and 412 are commonlycoupled to VSS via NMOS transistor 415, which is approximately half thesize of NMOS transistor 115 of input stage 110. NMOS transistor 416 hasmatching characteristics to transistor 415 and is coupled to receive anexternal bias current I₁ from a current source 417, which may be abandgap voltage generator. Transistor 416 is coupled in a currentmirroring arrangement to the gate of transistor 415 such that transistor415 sinks a current I₁. The gate of transistor 115, which is twice thesize of transistor 416, also has its gate coupled to the gate oftransistor 416 such that transistor 115 sinks a current 2I₁.

The drains of transistors 411 and 412 are commonly coupled to the drainof transistor 413. Transistor 413 has its gate commonly coupled to thegates of transistors 113 and 114 in a current mirroring arrangement suchthat the drain currents of transistor 113 and 114 are of the desiredvalue.

Transistor 420 and inverter 421 are provided such that the currentsources of input stage 110 are switched off to disable differentialcomparator 100 during power-down mode. Transistor 420 has its draincoupled to the gate of transistor 115, its source coupled to VSS, andits gate coupled to the output of inverter 421. Inverter 421 has itsinput coupled to receive enable signal EN. When the EN signal isdeasserted low, the output of inverter 421 is high such that transistor420 is switched on and the gate of transistor 115 is pulled towardsground. This results in all of the current sources 113, 114, and 115 ofinput stage 110 being switched off. Deasserting the EN signal alsotri-states input inverters 121 and 122. Cross-coupled inverters 123 and124 ensure that the inputs to inverters 131 and 132 are biased to alogic state. Thus, differential comparator 100 draws no current whileoperating in the power-down mode.

In the foregoing specification the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention.The specification and drawings are, accordingly, to be regarded in anillustrative rather than restrictive sense.

What is claimed is:
 1. A differential comparator comprising:a currentswitch having a pair of inputs coupled to receive a pair of small swingcomplementary input signals and a pair of complementary outputs thatoutput first complementary output signals having a voltage swingcentered about a predetermined voltage in response to the complementaryinput signals; and first and second inverters coupled to receive thefirst complementary output signals, wherein each inverter has a trippoint voltage .[.equal.]. .Iadd.corresponding .Iaddend.to thepredetermined voltage, the first and second inverters outputting secondcomplementary output signals in response to the first complementaryoutput signals, wherein the second complementary output signals are fullswing complementary output signals.
 2. The differential comparator ofclaim 1, wherein the current switch comprises:first and second matchedinput transistors coupled as a common source differential amplifier,wherein gates of the input transistors form the inputs of the currentswitch and drains of the input transistors form the outputs of thecurrent switch; first and second current sources coupled between therespective drains of the input transistors and an operating supplyvoltage; a third current source coupled between sources of the inputtransistors and system ground; and first and second resistors coupled inseries between the drains of the input transistors, wherein a commonnode between the first and second resistors is maintained at.Iadd.approximately .Iaddend.the trip point voltage of the first andsecond inverters.
 3. The differential comparator of claim 2, wherein anenable signal is provided to the differential comparator such that thedifferential comparator is enabled for normal operation when the enablesignal is asserted, the differential comparator further comprisingcircuitry for disabling the differential comparator in response to theenable signal being deasserted during a power-down mode of operationwherein the differential comparator draws no power.
 4. The differentialcomparator of claim 2, further comprising cross-coupled third and fourthinverters, wherein an input of the third inverter is coupled to anoutput of the first inverter and an output of the third inverter iscoupled to an output of the second inverter, and an input of the fourthinverter is coupled to the output of the second inverter and an outputof the fourth inverter is coupled to the output of the first inverter.5. The differential comparator of claim 4, further comprising fifth andsixth inverters having inputs coupled to the outputs of the first andsecond inverters, respectively, wherein the fifth and sixth invertersprovide additional gain.
 6. A differential comparator comprising:adifferential amplifier comprising a pair of inputs coupled to receive apair of small swing complementary input signals, a pair of outputs thatoutput first complementary output signals, and first and secondresistors coupled in series between the pair of outputs, wherein acommon node between the first and second resistors is maintained at apredetermined voltage such that an output swing of the differentialamplifier is centered about the predetermined voltage; and first andsecond inverters coupled to receive the first complementary outputsignals, wherein each inverter has a trip point voltage .[.equal.]..Iadd.corresponding .Iaddend.to the predetermined voltage, the first andsecond inverters outputting second complementary output signals inresponse to the first complementary output signals, wherein the secondcomplementary output signals are full swing complementary outputsignals.
 7. The differential comparator of claim 6, wherein an enablesignal is provided to the differential comparator such that thedifferential comparator is enabled for normal operation when the enablesignal is asserted, the differential comparator further comprisingcircuitry for disabling the differential comparator in response to theenable signal being deasserted during a power-down mode of operationwherein the differential comparator draws no power.
 8. The differentialcomparator of claim 6, further comprising cross-coupled third and fourthinverters, wherein an input of the third inverter is coupled to anoutput of the first inverter and an output of the third inverter iscoupled to an output of the second inverter, and an input of the fourthinverter is coupled to the output of the second inverter and an outputof the fourth inverter is coupled to the output of the first inverter.9. The differential comparator of claim 8, further comprising fifth andsixth inverters having inputs coupled to the outputs of the first andsecond inverters, respectively, wherein the fifth and sixth invertersprovide additional gain.
 10. A differential comparator comprising:adifferential amplifier comprising a pair of inputs coupled to receive apair of small swing complementary input signals, a pair of outputs thatoutput first complementary output signals and first and second resistorscoupled in series between the pair of outputs, wherein a common nodebetween the first and second resistors is maintained at a predeterminedvoltage such that an output swing of the differential amplifier iscentered about the predetermined voltage; first and second inverterscoupled to receive the first complementary output signals, wherein eachinverter has a trip point voltage .[.equal.]. .Iadd.corresponding.Iaddend.to the predetermined voltage, the first and second invertersoutputting second complementary output signals in response to the firstcomplementary output signals, wherein the second complementary outputsignals are full swing complementary output signals; cross-coupled thirdand fourth inverters, wherein an input of the third inverter is coupledto an output of the first inverter and an output of the third inverteris coupled to an output of the second inverter, and an input of thefourth inverter is coupled to the output of the second inverter and anoutput of the fourth inverter is coupled to the output of the firstinverter; and fifth and sixth inverters having inputs coupled to theoutputs of the first and second inverters, respectively, wherein thefifth and sixth inverters .[.provided.]. .Iadd.provide.Iaddend.additional gain.
 11. The differential comparator of claim 10,further comprising a seventh inverter having matching characteristics tothe first and second inverters, wherein an output of the seventhinverter is coupled to an input of the seventh inverter and the commonnode between the first and second resistors.
 12. A differentialcomparator comprising:a current switch having a pair of inputs coupledto receive a pair of small swing complementary input signals and a pairof outputs that output first complementary output signals having avoltage swing centered about a predetermined voltage in response to thecomplementary input signals; and first and second inverters coupled toreceive the first complementary output signals, wherein each inverterhas a trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to thepredetermined voltage, the first and second inverters outputting secondcomplementary output signals in response to the first complementaryoutput signals, wherein the second complementary output signals are fullswing complementary output signals; cross-coupled third and fourthinverters, wherein an input of the third inverter is coupled to anoutput of the first inverter and an output of the third inverter iscoupled to an output of the second inverter, and an input of the fourthinverter is coupled to the output of the second inverter and an outputof the fourth inverter is coupled to the output of the first inverter;and fifth and sixth inverters having inputs coupled to the outputs ofthe first and second inverters, respectively, wherein the fifth andsixth inverters provide additional gain.
 13. The differential comparatorof claim 12, further comprising first and second resistors coupled inseries between the pair of outputs of the current switch, wherein acommon node between the first and second resistors is maintained at thepredetermined voltage.
 14. The differential comparator of claim 13,further comprising a seventh inverter having matching characteristics tothe first and second inverters, wherein an output of the seventhinverter is coupled to an input of the seventh inverter and the commonnode between the first and second resistors.
 15. A method for generatingfull swing complementary signals from small swing complementary signalscomprising the steps of:generating complementary output signals having avoltage swing centered about a predetermined voltage in response to thesmall swing complementary signals; providing the complementary outputsignals to a pair of inverters each having a trip voltage .[.equal.]..Iadd.corresponding .Iaddend.to the predetermined voltage; andoutputting from the pair of inverters the full swing complementarysignals. .Iadd.16. The differential comparator of claim 1, furthercomprising cross-coupled third and fourth inverters, wherein an input ofthe third inverter is coupled to an output of the first inverter and anoutput of the third inverter is coupled to an output of the secondinverter, and an input of the fourth inverter is coupled to the outputof the second inverter and an output of the fourth inverter is coupledto the output of the first inverter..Iaddend..Iadd.17. A differentialcomparator comprising: a differential amplifier comprising a pair ofinputs coupled to receive a pair of small swing complementary inputsignals and a pair of complementary outputs that output firstcomplementary output signals having a voltage swing centered about apredetermined voltage in response to the complementary input signals;and first and second inverters coupled to receive the firstcomplementary output signals, wherein each inverter has a trip pointvoltage corresponding to the predetermined voltage, the first and secondinverters outputting second complementary output signals in response tothe first complementary output signals, wherein the second complementaryoutput signals are full swing complementary outputsignals..Iaddend..Iadd.18. The differential comparator of claim 17,wherein the differential amplifier includes first and second resistorscoupled in series between the pair of outputs, and a common node betweenthe first and second resistors is maintained at the predeterminedvoltage..Iaddend..Iadd.19. The differential comparator of claim 18,wherein the differential amplifier further includes:first and secondmatched input transistors coupled as a common source differentialamplifier, wherein gates of the input transistors form the inputs of thedifferential amplifier and drains of the input transistors form theoutputs of the differential amplifier; first and second current sourcescoupled between the respective drains of the input transistors and anoperating supply voltage; and a third current source coupled betweensources of the input transistors and system ground..Iaddend..Iadd.20.The differential comparator of claim 18, further comprisingcross-coupled third and fourth inverters, wherein an input of the thirdinverter is coupled to an output of the first inverter and an output ofthe third inverter is coupled to an output of the second inverter, andan input of the fourth inverter is coupled to the output of the secondinverter and an output of the fourth inverter is coupled to the outputof the first inverter..Iaddend.